Paper-Conference

MTST: A Multi-Task Scheduling Transformer Accelerator for Edge Computing

Transformer is pivotal in Large Language Models (LLMs), enabling superior performance in language tasks. However, the abundance of parameters poses a challenge for deploying …

zongcheng-yue

An Edge AI System Based on FPGA Platform for Railway Fault Detection

As the demands for railway transportation safety increase, traditional methods of rail track inspection no longer meet the needs of modern railway systems. To address the issues of …

jiale-li

A Mobile Computing-Friendly Stock Price Trend Prediction Model

In recent years, stock price trend prediction has been a hot topic in the field of AI for finance. Meanwhile, with the constant fluctuations in financial markets, investors …

zhihang-liu

A Framework for Mapping Convolutional Neural Network onto Memristor Crossbars

The processing-in-memory architecture based on memristors has been widely studied for hardware implementation in neural networks, serving as a solution to address the von Neumann …

jiale-li

ViT-LOB: Efficient Vision Transformer for StockPrice Trend Prediction Using Limit Order Books

Predicting stock price trends in High-frequency trading (HFT) demands utmost time sensitivity and resource efficiency. Previous research has stacked attention mechanisms with …

zhihang-liu

PQDE: Comprehensive Progressive Quantization with Discretization Error for Ultra-Low Bitrate MobileNet towards Low-Resolution Imagery

In deep learning, quantization is employed to tackle deployment challenges of neural networks in resource-limited environments like mobile and edge devices. Traditional …

zongcheng-yue

Early-Stopped Technique for BCH Decoding Algorithm Under Tolerant Fault Probability

In this paper, a technique for the Berlekamp-Massey(BM) algorithm is provided to reduce the latency of decoding and save decoding power by early termination or early-stopped …

shih-shuan-wang

Implementation for JSCC Scheme Based on QC-LDPC Codes

Joint Souce-Channel Code based on QC-LDPC codes on the FPGA platform

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Dr Sean Longyu Ma

CNN Accelerator with Non-Blocking Network Design

We designed a new hardware architecture that uses a non-blocking network for accelerating the convolutional neural network (CNN)

chun-yan-lo

A highly integrated RISC-V based SoC for on-board unit in ETC system

A highly integrated system-on-chip for the on-board unit in the electronic toll collection system is presented.

xinchao-zhong