MTST: A Multi-Task Scheduling Transformer Accelerator for Edge Computing

Transformer is pivotal in Large Language Models (LLMs), enabling superior performance in language tasks. However, the abundance of parameters poses a challenge for deploying Transformer on resource-constrained edge devices for edge computing, such as Field-Programmable Gate Arrays (FPGAs). To overcome this limitation, we present an FPGA-based architecture that enables high-performance deployment of Transformer for edge computing, incorporating a unique multitask ping-pong scheme. To strike a balance between computing efficiency and logic resource consumption, we adopt a systolic array as a reusable processing engine (PE), employing meticulous space exploration techniques to determine the optimal quantity and dimensions of PEs within a given resource budget for our architecture. We implement the architecture on ZCU 102 FPGA platform, the experimental results illustrate that the proposed accelerator achieves state-of-the-art performance while consuming fewer resources. Recommended citation:

@INPROCEEDINGS{10760930, author={Yue, Zongcheng and Yan, Dongwei and Wu, Ran and Ma, Longyu and Sham, Chiu-Wing}, booktitle={2024 IEEE 13th Global Conference on Consumer Electronics (GCCE)}, title={MTST: A Multi-Task Scheduling Transformer Accelerator for Edge Computing}, year={2024}, volume={}, number={}, pages={1394-1395}, keywords={Performance evaluation;Processor scheduling;Computer architecture;Transformer cores;Transformers;Multitasking;Systolic arrays;Space exploration;Field programmable gate arrays;Edge computing;Transformer;FPGA;Hardware Accelerator}, doi={10.1109/GCCE62371.2024.10760930}}