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A list of all the posts and pages found on the site. For you robots out there is an XML version available for digesting as well.
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Posts
Visit Shanghai Jiao Tong University
Published:
Dr. Sean Ma was invited to visit The Digital System and Chip Research and Design Center, Shanghai Jiao Tong University from November 1, 2024, to November 30, 2024
Team building (PhD Research Group)
Published:
Team building (BBQ) within our PhD research group. The location is One Tree Hill, Auckland, New Zealand
Invitation to McSoC2023
Published:
I was invited to attend McSoC 2023 in Singapore.
Team building (PhD Research Group)
Published:
Team building within our PhD research group. The location is Piha, Auckland, New Zealand
portfolio
Evaluation of Processor Architecture for Engine Control Unit on Motorcycle
Published:
Co-Principal Investigator (Jan 2024 - Jun 2024, NZD 64,309)
Evaluation of RISC-V Architecture for Engine Control Unit on Motorcycle
Published:
Co-Principal Investigator(Sep 2023 - Dec 2023, NZD 44,092) 
publications
Optimized layer architecture for layered LDPC code decoder
Published in 2018 International Conference on Advanced Technologies for Communications (ATC), 2018
We proposed an optimized BPU to perform all the operations of check nodes and variable nodes of a QC-LDPC decoder.
Recommended citation: Ma, L., & Sham, C. W. (2018, October). Optimized layer architecture for layered LDPC code decoder. In 2018 International Conference on Advanced Technologies for Communications (ATC) (pp. 287-291). IEEE. https://ieeexplore.ieee.org/abstract/document/8587568/
A novel data packing technique for QC-LDPC decoder architecture applied to NAND flash controller
Published in 2019 IEEE 8th Global Conference on Consumer Electronics (GCCE), 2019
This paper presents a data packing technique for Quasi-Cyclic LDPC codes decoder applied to NAND flash controller.
Recommended citation: Ma, L., Chou, H. F., & Sham, C. W. (2019, October). A novel data packing technique for QC-LDPC decoder architecture applied to NAND flash controller. In 2019 IEEE 8th Global Conference on Consumer Electronics (GCCE) (pp. 897-898). IEEE. https://ieeexplore.ieee.org/abstract/document/9015393/
A real-time flexible telecommunication decoding architecture using FPGA partial reconfiguration
Published in IEEE Transactions on Circuits and Systems II: Express Briefs, 2019
A real-time reconfigurable decoding architecture is introduced to alleviate high computational complexity and power consumption
Recommended citation: Ma, L., Sham, C. W., Sun, J., & Tenorio, R. V. (2019). A real-time flexible telecommunication decoding architecture using fpga partial reconfiguration. IEEE Transactions on Circuits and Systems II: Express Briefs, 67(10), 2149-2153. https://ieeexplore.ieee.org/abstract/document/8906146/
SoC-FPGA-based implementation of iris recognition enhanced by QC-LDPC codes
Published in 2019 International Conference on Field-Programmable Technology (ICFPT), 2019
We focus on an iris recognition system implementation with an error correction scheme, namely QC-LDPC
Recommended citation: Ma, L., & Sham, C. W. (2019, December). Soc-fpga-based implementation of iris recognition enhanced by qc-ldpc codes. In 2019 International Conference on Field-Programmable Technology (ICFPT) (pp. 391-394). IEEE. https://ieeexplore.ieee.org/abstract/document/8977863/
Iris recognition system implementation improved by QC-LDPC codes
Published in 2020 IEEE 2nd Global Conference on Life Sciences and Technologies (LifeTech), 2020
An iris recognition system is implemented with certain LDPC codes which have the ability to correct intrinsic fuzziness.
Recommended citation: Ma, L., & Sham, C. W. (2020, March). Iris recognition system implementation improved by qc-ldpc codes. In 2020 IEEE 2nd Global Conference on Life Sciences and Technologies (LifeTech) (pp. 88-99). IEEE. https://ieeexplore.ieee.org/abstract/document/9081256/
A Novel Iris Verification Framework Using Machine Learning algorithm on Embedded Systems
Published in 2020 IEEE 9th Global Conference on Consumer Electronics (GCCE), 2020
We propose a new iris verification framework for an embedded system which uses IrisMatch-CNN as feature extraction and classification.
Recommended citation: Lo, C. Y., Sham, C. W., & Ma, L. (2020, October). A Novel Iris Verification Framework Using Machine Learning algorithm on Embedded Systems. In 2020 IEEE 9th Global Conference on Consumer Electronics (GCCE) (pp. 173-175). IEEE. https://ieeexplore.ieee.org/abstract/document/9291908/
An iris recognition system implementation with error correction capability by reusing WiFi standard LDPC codes
Published in 2020 IEEE 9th Global Conference on Consumer Electronics (GCCE), 2020
The paper proposes a method to reuse IEEE 802.11n LDPC codes onto an iris recognition system based on an embedded device.
Recommended citation: Ma, L., Zhong, X., Sham, C. W., & Lo, C. Y. (2020, October). An iris recognition system implementation with error correction capability by reusing WiFi standard LDPC codes. In 2020 IEEE 9th Global Conference on Consumer Electronics (GCCE) (pp. 265-267). IEEE. https://ieeexplore.ieee.org/abstract/document/9291859/
A RISC-V SoC for mobile payment based on visible light communication
Published in 2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2020
A RISC-V SoC (system on chip) based on visible light communication (VLC) for mobile payment application is presented.
Recommended citation: Zhong, X., Sham, C. W., & Ma, L. (2020, December). A risc-v soc for mobile payment based on visible light communication. In 2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) (pp. 102-105). IEEE. https://ieeexplore.ieee.org/abstract/document/9301688/
CNN Accelerator with Non-Blocking Network Design
Published in 2021 IEEE 10th Global Conference on Consumer Electronics (GCCE), 2021
We designed a new hardware architecture that uses a non-blocking network for accelerating the convolutional neural network (CNN)
Recommended citation: Lo, C. Y., Ma, L., & Sham, C. W. (2021, October). CNN Accelerator with Non-Blocking Network Design. In 2021 IEEE 10th Global Conference on Consumer Electronics (GCCE) (pp. 813-815). IEEE. https://ieeexplore.ieee.org/abstract/document/9622107/
A highly integrated RISC-V based SoC for on-board unit in ETC system
Published in 2021 IEEE 10th Global Conference on Consumer Electronics (GCCE), 2021
A highly integrated system-on-chip for the on-board unit in the electronic toll collection system is presented.
Recommended citation: Zhong, X., Sham, C. W., & Ma, L. (2021, October). A highly integrated risc-v based soc for on-board unit in etc system. In 2021 IEEE 10th Global Conference on Consumer Electronics (GCCE) (pp. 302-303). IEEE. https://ieeexplore.ieee.org/abstract/document/9622039/
A dynamically reconfigurable QC-LDPC implementation for iris recognition
Published in 2021 IEEE 10th Global Conference on Consumer Electronics (GCCE), 2021
Extracting and analyzing iris textures for biometric recognition has been extensively studied.
Recommended citation: Ma, L., Sham, C. W., Lo, C. Y., & Zhong, X. (2021, October). A dynamically reconfigurable qc-ldpc implementation for iris recognition. In 2021 IEEE 10th Global Conference on Consumer Electronics (GCCE) (pp. 808-812). IEEE. [https://ieeexplore.ieee.org/abstract/document/9622039/](https://ieeexplore.ieee.org/abstract/document/9622068/)
An effective multi-mode iris authentication system on a microprocessor-FPGA heterogeneous platform with QC-LDPC codes
Published in IEEE Access, 2021
Multiple iris recognition algorithm implemented on an SoC-FPGA platform
Recommended citation: Ma, L., Sham, C. W., Lo, C. Y., & Zhong, X. (2021). An effective multi-mode iris authentication system on a microprocessor-fpga heterogeneous platform with qc-ldpc codes. IEEE Access, 9, 163665-163674. https://ieeexplore.ieee.org/abstract/document/9642996/
Implementation for JSCC Scheme Based on QC-LDPC Codes
Published in 2022 IEEE 11th Global Conference on Consumer Electronics (GCCE), 2022
Joint Souce-Channel Code based on QC-LDPC codes on the FPGA platform
Recommended citation: Ma, L., Sham, C. W., Zhan, J., & Lau, F. C. (2022, October). Implementation for JSCC Scheme Based on QC-LDPC Codes. In 2022 IEEE 11th Global Conference on Consumer Electronics (GCCE) (pp. 292-295). IEEE. https://ieeexplore.ieee.org/abstract/document/10014340
Joint Source-Channel Coding System for 6G Communication: Design, Prototype and Future Directions
Published in IEEE Access, 2024
This paper is about JSCC implementation for 6G.
Recommended citation: Zhong, X., Sham, C. W., Ma, S. L., Chou, H. F., Mostaani, A., Vu, T. X., & Chatzinotas, S. (2024). Joint Source-Channel Coding System for 6G Communication: Design, Prototype and Future Directions. IEEE Access. https://ieeexplore.ieee.org/abstract/document/10416847
Early-Stopped Technique for BCH Decoding Algorithm Under Tolerant Fault Probability
Published in International Congress on Information and Communication Technology, 2024
Recommended citation: Wang, SS., Chou, Hf., Zhong, X., Ma, S.L. (2024). Early-Stopped Technique for BCH Decoding Algorithm Under Tolerant Fault Probability. In: Yang, XS., Sherratt, S., Dey, N., Joshi, A. (eds) Proceedings of Ninth International Congress on Information and Communication Technology. ICICT 2024 2024. Lecture Notes in Networks and Systems, vol 1002. Springer, Singapore. https://doi.org/10.1007/978-981-97-3299-9_3 https://link.springer.com/chapter/10.1007/978-981-97-3299-9_3
Urban Aquatic Scene Expansion for Semantic Segmentation in Cityscapes
Published in MDPI, 2024
Recommended citation: Yue Z, Lo C-Y, Wu R, Ma L, Sham C-W. Urban Aquatic Scene Expansion for Semantic Segmentation in Cityscapes. Urban Science. 2024; 8(2):23. https://www.mdpi.com/2413-8851/8/2/23
PQDE: Comprehensive Progressive Quantization with Discretization Error for Ultra-Low Bitrate MobileNet towards Low-Resolution Imagery
Published in 2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS), 2024
Recommended citation: Z. Yue, R. Wu, L. Ma, C. Fu and C. -W. Sham, "PQDE: Comprehensive Progressive Quantization with Discretization Error for Ultra-Low Bitrate MobileNet towards Low-Resolution Imagery," 2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS), Abu Dhabi, United Arab Emirates, 2024 https://ieeexplore.ieee.org/abstract/document/10595949/
ViT-LOB: Efficient Vision Transformer for StockPrice Trend Prediction Using Limit Order Books
Published in 2024 10th International Conference on Applied System Innovation (ICASI), 2024
Recommended citation: Z. Liu, C. -W. Sham, L. Ma and C. Fu, "ViT-LOB: Efficient Vision Transformer for StockPrice Trend Prediction Using Limit Order Books," 2024 10th International Conference on Applied System Innovation (ICASI), Kyoto, Japan, 2024 https://ieeexplore.ieee.org/abstract/document/10547868
talks
WebVM - an innovative approach to teaching OS concepts
Published:
Elliott Wen (the major contributor) and I have developed a home-grown teaching tool, WebVM, for operating system courses. WebVM provides students instant access to an Ubuntu Linux operating system in their browser. Students have full admin access to the OS, allowing them to develop system kernel modules. Other related products such as Flexit or Coderunner won’t allow this. For SOFTENG 370 in 2024 Sem 1, we received overwhelmingly positive feedback (4.43) from the students. Many praised the effectiveness of WebVM in helping them learn important operating system concepts and practical system development skills. Students particularly enjoyed one assignment, which involved creating a Linux kernel module to control a virtual LED panel and draw a picture they like.
Joint 6G-PHYSEC & INTERACT Workshop on 6G Technologies and PHY Layer Security
Published:
Topic: Empirical Risk-aware Machine Learning on Trojan-Horse Detection for Trusted Quantum Key Distribution Networks
teaching
UoA Postgraduate Supervision experience
Postgraduate supervision, The University of Auckland, School of Computer Science, 2023
Doctor of Philosophy in Computer Science
Jiale Li (2023- Now)
The Computer Architecture for Edge Artificial Intelligence
Zhihang Liu (2023- Now)
Hardware Acceleration of Deep-learning Algorithm on FPGA for Edge Device
Zongcheng Yue (2022- Now)
Computational Architecture for Intelligent Edge Computing
Brian Zhong (2019- Now)
A Comprehensive Study on RISC-V’s Applications to AIoT Endpoint SoCs
Master of Science (Research)
Yulin Fu (2024- Now)
FPGA-Adapted Neural Network Models for Low-Latency, High-Accuracy Image recognition: An Integrated Approach
Dongwei Yan (2024- Now)
Effective Progressive Quantization: Enhancing Residual Neural Networks with Ultra-Low Precision Validation on ResNet18 and ResNet50
Master of Information and Technology (Internship)
Han(Olivia) Li (2023-2024)
Roshan Shaheen (2023-2024)
Rupak Lingwal (2023-2024)
UoA Undergraduate Teaching experience
Undergraduate course, The University of Auckland, School of Computer Science, 2023