Dr.Sean Ma

Dr.Sean Ma

Lecturer/PhD Supervisor/IC Design Engineer/Husband

Publications

A Review of FPGA-Driven LLM Acceleration

Published in 2025 IEEE 18th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), 2025

Recommended citation: Y. Fu, J. Li, C. Cheng, S. L. Ma, C. -W. Sham and N. Zou, "A Review of FPGA-Driven LLM Acceleration," 2025 IEEE 18th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Singapore, Singapore, 2025, pp. 49-52 https://ieeexplore.ieee.org/document/11310915

Published in , 2026

LHA: Layer-wise Hardware Acceleration of Progressive Quantizing Inference through Partial Reconfiguration for Edge Computing

Published in 2025 International Joint Conference on Neural Networks (IJCNN), 2025

Recommended citation: Z. Yue, S. L. Ma, C. -W. Sham and C. Fu, "LHA: Layer-wise Hardware Acceleration of Progressive Quantizing Inference through Partial Reconfiguration for Edge Computing," 2025 International Joint Conference on Neural Networks (IJCNN), Rome, Italy, 2025, pp. 1-8 https://ieeexplore.ieee.org/document/11229400

KernelVM: Teaching Linux Kernel Programming through a Browser-Based Virtual Machine

Published in Proceedings of the 56th ACM Technical Symposium on Computer Science Education V. 1, 2025

Recommended citation: Wen, E., Ma, S., Denny, P., Tempero, E., Weber, G., & Yue, Z. (2025, February). KernelVM: Teaching Linux Kernel Programming through a Browser-Based Virtual Machine. In Proceedings of the 56th ACM Technical Symposium on Computer Science Education V. 1 (pp. 1204-1210). https://dl.acm.org/doi/abs/10.1145/3641554.3701831

A Framework for Mapping Convolutional Neural Network onto Memristor Crossbars

Published in 2024 IEEE 13th Global Conference on Consumer Electronics (GCCE), 2024

Recommended citation: J. Li, Y. Fu, C. -W. Sham and S. L. Ma, "A Framework for Mapping Convolutional Neural Network onto Memristor Crossbars," 2024 IEEE 13th Global Conference on Consumer Electronics (GCCE), Kitakyushu, Japan, 2024, pp. 1390-1393, doi: 10.1109/GCCE62371.2024.10760655. https://ieeexplore.ieee.org/abstract/document/10760655

PQDE: Comprehensive Progressive Quantization with Discretization Error for Ultra-Low Bitrate MobileNet towards Low-Resolution Imagery

Published in 2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS), 2024

Recommended citation: Z. Yue, R. Wu, L. Ma, C. Fu and C. -W. Sham, "PQDE: Comprehensive Progressive Quantization with Discretization Error for Ultra-Low Bitrate MobileNet towards Low-Resolution Imagery," 2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS), Abu Dhabi, United Arab Emirates, 2024 https://ieeexplore.ieee.org/abstract/document/10595949/

Early-Stopped Technique for BCH Decoding Algorithm Under Tolerant Fault Probability

Published in International Congress on Information and Communication Technology, 2024

Recommended citation: Wang, SS., Chou, Hf., Zhong, X., Ma, S.L. (2024). Early-Stopped Technique for BCH Decoding Algorithm Under Tolerant Fault Probability. In: Yang, XS., Sherratt, S., Dey, N., Joshi, A. (eds) Proceedings of Ninth International Congress on Information and Communication Technology. ICICT 2024 2024. Lecture Notes in Networks and Systems, vol 1002. Springer, Singapore. https://doi.org/10.1007/978-981-97-3299-9_3 https://link.springer.com/chapter/10.1007/978-981-97-3299-9_3

A dynamically reconfigurable QC-LDPC implementation for iris recognition

Published in 2021 IEEE 10th Global Conference on Consumer Electronics (GCCE), 2021

Extracting and analyzing iris textures for biometric recognition has been extensively studied.

Recommended citation: Ma, L., Sham, C. W., Lo, C. Y., & Zhong, X. (2021, October). A dynamically reconfigurable qc-ldpc implementation for iris recognition. In 2021 IEEE 10th Global Conference on Consumer Electronics (GCCE) (pp. 808-812). IEEE. [https://ieeexplore.ieee.org/abstract/document/9622039/](https://ieeexplore.ieee.org/abstract/document/9622068/)

A highly integrated RISC-V based SoC for on-board unit in ETC system

Published in 2021 IEEE 10th Global Conference on Consumer Electronics (GCCE), 2021

A highly integrated system-on-chip for the on-board unit in the electronic toll collection system is presented.

Recommended citation: Zhong, X., Sham, C. W., & Ma, L. (2021, October). A highly integrated risc-v based soc for on-board unit in etc system. In 2021 IEEE 10th Global Conference on Consumer Electronics (GCCE) (pp. 302-303). IEEE. https://ieeexplore.ieee.org/abstract/document/9622039/

CNN Accelerator with Non-Blocking Network Design

Published in 2021 IEEE 10th Global Conference on Consumer Electronics (GCCE), 2021

We designed a new hardware architecture that uses a non-blocking network for accelerating the convolutional neural network (CNN)

Recommended citation: Lo, C. Y., Ma, L., & Sham, C. W. (2021, October). CNN Accelerator with Non-Blocking Network Design. In 2021 IEEE 10th Global Conference on Consumer Electronics (GCCE) (pp. 813-815). IEEE. https://ieeexplore.ieee.org/abstract/document/9622107/

A RISC-V SoC for mobile payment based on visible light communication

Published in 2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2020

A RISC-V SoC (system on chip) based on visible light communication (VLC) for mobile payment application is presented.

Recommended citation: Zhong, X., Sham, C. W., & Ma, L. (2020, December). A risc-v soc for mobile payment based on visible light communication. In 2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) (pp. 102-105). IEEE. https://ieeexplore.ieee.org/abstract/document/9301688/

An iris recognition system implementation with error correction capability by reusing WiFi standard LDPC codes

Published in 2020 IEEE 9th Global Conference on Consumer Electronics (GCCE), 2020

The paper proposes a method to reuse IEEE 802.11n LDPC codes onto an iris recognition system based on an embedded device.

Recommended citation: Ma, L., Zhong, X., Sham, C. W., & Lo, C. Y. (2020, October). An iris recognition system implementation with error correction capability by reusing WiFi standard LDPC codes. In 2020 IEEE 9th Global Conference on Consumer Electronics (GCCE) (pp. 265-267). IEEE. https://ieeexplore.ieee.org/abstract/document/9291859/

A Novel Iris Verification Framework Using Machine Learning algorithm on Embedded Systems

Published in 2020 IEEE 9th Global Conference on Consumer Electronics (GCCE), 2020

We propose a new iris verification framework for an embedded system which uses IrisMatch-CNN as feature extraction and classification.

Recommended citation: Lo, C. Y., Sham, C. W., & Ma, L. (2020, October). A Novel Iris Verification Framework Using Machine Learning algorithm on Embedded Systems. In 2020 IEEE 9th Global Conference on Consumer Electronics (GCCE) (pp. 173-175). IEEE. https://ieeexplore.ieee.org/abstract/document/9291908/

Iris recognition system implementation improved by QC-LDPC codes

Published in 2020 IEEE 2nd Global Conference on Life Sciences and Technologies (LifeTech), 2020

An iris recognition system is implemented with certain LDPC codes which have the ability to correct intrinsic fuzziness.

Recommended citation: Ma, L., & Sham, C. W. (2020, March). Iris recognition system implementation improved by qc-ldpc codes. In 2020 IEEE 2nd Global Conference on Life Sciences and Technologies (LifeTech) (pp. 88-99). IEEE. https://ieeexplore.ieee.org/abstract/document/9081256/

SoC-FPGA-based implementation of iris recognition enhanced by QC-LDPC codes

Published in 2019 International Conference on Field-Programmable Technology (ICFPT), 2019

We focus on an iris recognition system implementation with an error correction scheme, namely QC-LDPC

Recommended citation: Ma, L., & Sham, C. W. (2019, December). Soc-fpga-based implementation of iris recognition enhanced by qc-ldpc codes. In 2019 International Conference on Field-Programmable Technology (ICFPT) (pp. 391-394). IEEE. https://ieeexplore.ieee.org/abstract/document/8977863/

A real-time flexible telecommunication decoding architecture using FPGA partial reconfiguration

Published in IEEE Transactions on Circuits and Systems II: Express Briefs, 2019

A real-time reconfigurable decoding architecture is introduced to alleviate high computational complexity and power consumption

Recommended citation: Ma, L., Sham, C. W., Sun, J., & Tenorio, R. V. (2019). A real-time flexible telecommunication decoding architecture using fpga partial reconfiguration. IEEE Transactions on Circuits and Systems II: Express Briefs, 67(10), 2149-2153. https://ieeexplore.ieee.org/abstract/document/8906146/

A novel data packing technique for QC-LDPC decoder architecture applied to NAND flash controller

Published in 2019 IEEE 8th Global Conference on Consumer Electronics (GCCE), 2019

This paper presents a data packing technique for Quasi-Cyclic LDPC codes decoder applied to NAND flash controller.

Recommended citation: Ma, L., Chou, H. F., & Sham, C. W. (2019, October). A novel data packing technique for QC-LDPC decoder architecture applied to NAND flash controller. In 2019 IEEE 8th Global Conference on Consumer Electronics (GCCE) (pp. 897-898). IEEE. https://ieeexplore.ieee.org/abstract/document/9015393/

Optimized layer architecture for layered LDPC code decoder

Published in 2018 International Conference on Advanced Technologies for Communications (ATC), 2018

We proposed an optimized BPU to perform all the operations of check nodes and variable nodes of a QC-LDPC decoder.

Recommended citation: Ma, L., & Sham, C. W. (2018, October). Optimized layer architecture for layered LDPC code decoder. In 2018 International Conference on Advanced Technologies for Communications (ATC) (pp. 287-291). IEEE. https://ieeexplore.ieee.org/abstract/document/8587568/